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Stacked CMOS Sensor

 
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mawyatt



Joined: 22 Aug 2013
Posts: 1394
Location: Clearwater

PostPosted: Sat Feb 24, 2018 8:00 pm    Post subject: Stacked CMOS Sensor Reply with quote

Just returned from a weeklong IEEE conference out west where Sony has introduced a new type CMOS sensor. It's based on 3 separate wafers that are bonded together to form a stacked sensor. Wasn't sure if this was public yet (IEEE has strict rules), but found this site 2/3/2018 which dates back to 2017 for technology info.

Here's a link to the technology and some sample images & video.

https://fuse.wikichip.org/news/763/iedm-2017-sonys-3-layer-stacked-cmos-image-sensor-technology/


There's more to it than revealed on this site, but this is a good reference for the general technology idea.

Edit. I found the new reference that is public now.

https://www.sony.net/SonyInfo/News/Press/201802/18-018E/index.html

This uses the stacking wafer technique previously mentioned and places a 14 bit analog to digital converter (ADC) under each pixel!!! The demo chip has 1.46 million 14 bit ADCs and achieves 660 fps!!

Best,
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