Chip Image @ 16218 by 11554

Images taken in a controlled environment or with a posed subject. All subject types.

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Saul
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Post by Saul »

mawyatt wrote:I created a completely new folder, so maybe this will allow downloading and zooming.

http://img.gg/yZNjmZ2

Best,

Mike
Download - yes. What a great stack'n'stitch photo !
Zooming - still no :(
Saul
μ-stuff

rjlittlefield
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Post by rjlittlefield »

I get the same result as Saul: download OK, no zoom.

This is very nice work!

I do see a couple of areas where the grid appears to show alignment errors.

Can you tell us again, please, exactly how you shot and processed this image? What optics and what alignment settings?

Also, do you happen to still have the .zsj files for each of the tiles?

If so, then I would be interested to receive copies of those, at support@zerenesystems.com .

I am thinking there may be some way for me to change or add functionality in Zerene Stacker to help with the alignment issues.

--Rik

mawyatt
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Location: Clearwater, Florida

Post by mawyatt »

Chris, Saul, Rik,

Not sure how to get zoom working, but al least you can download now.

Thanks for all the help, sorry it took me so long.

Best,
Research is like a treasure hunt, you don't know where to look or what you'll find!
~Mike

mawyatt
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Joined: Thu Aug 22, 2013 6:54 pm
Location: Clearwater, Florida

Post by mawyatt »

rjlittlefield wrote:I get the same result as Saul: download OK, no zoom.

This is very nice work!

I do see a couple of areas where the grid appears to show alignment errors.

Can you tell us again, please, exactly how you shot and processed this image? What optics and what alignment settings?

Also, do you happen to still have the .zsj files for each of the tiles?

If so, then I would be interested to receive copies of those, at support@zerenesystems.com .

I am thinking there may be some way for me to change or add functionality in Zerene Stacker to help with the alignment issues.

--Rik
This was done this past summer, and an initial try at large stitches. 16 separate stacked images were utilized, but #13 & #14 redone adding 5 additional sessions (3 for #13 and 2 for #14). So a total of 21 sessions all together. Stack length was 250~400 images.

The camera was a Nikon D500 and lens a Mitutoyo 10X infinite with a Nikon 200mm F4 tube lens. Setup was horizontal using a Stackshot controller under Zerene UI, with a modified THK KR20 focus rail. Lighting was provided by ~5 strobes and dual light tents, may have used a styrofoam cup also.

Stacking was in Zerene, but I can't remember the parameters. Stitching was done with PS. I do recall PS having lots of issues and this was a bear to get put together, ending up having to stitch smaller sections, then stitch the smaller sections into the final rendering.

Recall the overall effort took a couple weeks to complete.

I'll try and send those files over.

Best,
Research is like a treasure hunt, you don't know where to look or what you'll find!
~Mike

mawyatt
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Joined: Thu Aug 22, 2013 6:54 pm
Location: Clearwater, Florida

Post by mawyatt »

Someone on another forum asked if I could help identify some of the components on these chip images, thought this might be useful to the folks here too, so here are my notes.

"I'll try and describe some components. You can wander around from image to image and you'll notice something that looks like tiny spherical mirrors (AtlasTC2, FGUTC2, RXP1 and solder ball images), these are solder balls (40 & 100 micron dia) for electrical attachment (flip chip upside "down" mounting). The octagonal spirals, these are inductors or transformers, the gold tiny filaments (DD2A) are 25 micron diameter gold wire bonds for electrical connection. The tiny amber or brown squares you see on many images covering most of the image areas is metal fill patterns to help planarize the surface during chip processing, the tiny multifingered areas beneath the chip surface are interdigital capacitors. The larger continuous surfaces are metal lines, some on the surface and some imbedded beneath. The actual transistors are very tiny, if you look at the InP chip images you can vaguely make out the HBT transistors where the subsurface very thin multiple metal lines converge, usually 3. The bright large square areas in gold or silver (Aluminum) are bond pads, this is where electrical attachments are made with wirebonds. If you look very closely at some images (InP RF Detector) with the bond pads you can see some skid marks, these are where probes were used during wafer scale testing (chips were not sawed from the wafer yet). Wafers are how chips are batch manufactured before dicing into individual chips, you can see some very old 6" wafer images (today wafers are mostly 12", and heading to 16" diameter).

Anyway, hope this helps with the component identification."

Best,

Edit added "down" above.
Last edited by mawyatt on Mon Feb 05, 2018 9:07 am, edited 1 time in total.
Research is like a treasure hunt, you don't know where to look or what you'll find!
~Mike

ChrisR
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Post by ChrisR »

That adds a lot of interest, thanks Mike.
Chris R

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